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AX88170 L USB to Fast Ethernet/HomePNA Controller
USB to Fast Ethernet/HomePNA Controller
Document No.: AX170-12 / V1.2 / Apr. 11 '01
Features
* * * * * * * * * * * Single chip USB to 10/100Mbps Fast Ethernet and 1/10Mbps HomePNA Network Controller Compliant with USB specification 1.0 and 1.1 Full Speed USB Device with bus power capability USB Communication Class Spec 1.0 Compliant Support 4 endpoints on USB IEEE 802.3u 100BASE-T, TX, and T4 Compatible Embedded 5K*16 bit SRAM Support both full-duplex or half-duplex operation on Fast Ethernet Provides a MII port for both Ethernet and HomePNA PHY interface Supports suspended mode and remote wakeup (link_up or magic packet) Optional PHY power down mode for power saving * * * * * * Provides optional MII/RMII interface with PHY mode for multiple ports USB-to-USB bridge application. Support 256/512 bytes serial EEPROM (used for saving USB Descriptors) Support automatic loading of Ethernet ID, USB Descriptors and Adapter Configuration from EEPROM on power-on initialization External PHY loop-back diagnostic capability Small form factor 64-pin LQFP package 48MHz and 25MHz Operation, pure 3.3V operation with I/O 5V tolerance
*IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respect ive holders.
Product description
The AX88170 USB to Fast Ethernet/HomePNA Controller is a high performance and highly integrated Controller with embedded 5K*16 bit SRAM. The AX88170 contains a USB interface to host CPU and compliant with USB Standard V1.0 and V1.1. The interface between AX88170 and PC Host is compliant with USB Communication Class Specification 1.0. The AX88170 could be used for both 10M/100Mbps Fast Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and 1M/10M HomePNA standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII) interface to simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional MII/RMII interface with PHY mode, combine with Ethernet repeater or switch IC can build a multiple ports USB-to-USB bridge application.
System Block Diagram
RJ45
RJ11
MAGNETIC
MAGNETIC
10/100 Mbps Ethernet PHY/TxRx
1/10 Mbps Home LAN PHY
AX88170
EEPROM
USB I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Frist Released Date : Sep/11/2000
http://www.asix.com.tw
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558
CONFIDENTIAL
AX88170 CONTENTS
PRELIMINARY
1.0 INTRODUCTION ...........................................................................................................................................................................4 1.1 GENERAL DESCRIPTION:............................................................................................................................................................ 4 1.2 AX88170 BLOCK DIAGRAM: ...................................................................................................................................................... 4 1.3 AX88170 PIN CONNECTION DIAGRAM WITH MII INTERFACE ........................................................................................... 5 1.4 AX88170 PIN CONNECTION DIAGRAM WITH RMII INTERFACE......................................................................................... 6 2.0 SIGNAL DESCRIPTION...............................................................................................................................................................7 2.1 USB BUS INTERFACE SIGNALS GROUP .................................................................................................................................... 7 2.2 EEPROM SIGNALS GROUP ......................................................................................................................................................... 7 2.3A MII INTERFACE SIGNALS GROUP (MAC MODE) .................................................................................................................. 7 2.3B MII INTERFACE SIGNALS GROUP (PHY MODE)..................................................................................................................... 8 2.4 RMII INTERFACE SIGNAL PINS (PHY MODE) .......................................................................................................................... 9 2.5 MISCELLANEOUS PINS GROUP................................................................................................................................................... 9 3.0 EEPROM MEMORY MAPPING...............................................................................................................................................11 4.0 USB COMMANDS .......................................................................................................................................................................12 4.1 USB STANDARD COMMANDS................................................................................................................................................... 12 4.2 USB COMMUNICATION CLASS COMMANDS......................................................................................................................... 13 4.3 USB VENDOR COMMANDS....................................................................................................................................................... 14 5.0 USB CONFIGURATION STRUCTURE...................................................................................................................................16 5.1 USB CONFIGURATION. ............................................................................................................................................................. 16 5.2 USB INTERFACE CLASS. ........................................................................................................................................................... 16 5.3 USB ENDPOINTS........................................................................................................................................................................ 16 6.0 ELECTRICAL SPECIFICATION AND TIMINGS .................................................................................................................17 6.1 ABSOLUTE MAXIMUM RATINGS............................................................................................................................................ 17 6.2 GENERAL OPERATION CONDITIONS...................................................................................................................................... 17 6.3 DC CHARACTERISTICS.............................................................................................................................................................. 17 6.4 A.C. TIMING CHARACTERISTICS............................................................................................................................................. 18 6.4.1 25M_XIN............................................................................................................................................................................18 6.4.2 48M_XIN............................................................................................................................................................................18 6.4.3 Reset Timing......................................................................................................................................................................18 6.4.4 MII Timing of MAC mode................................................................................................................................................20 6.4.5 MII Timing of PHY mode .................................................................................................................................................21 6.4.6 RMII Interface Timing of PHY Mode.............................................................................................................................22 6.4.7 STATION MANAGEMENT TIMING..............................................................................................................................23 6.4.8 SERIAL EEPROM TIMING.............................................................................................................................................24 7.0 PACKAGE INFORMATION.......................................................................................................................................................25 APPENDIX A: SYSTEM APPLICATIONS ....................................................................................................................................26 A.1 USB TO FAST ETHERNET CONVERTER................................................................................................................................ 26 A.2 USB TO FAST ETHERNET AND/OR HOMELAN COMBO SOLUTION ................................................................................ 27 A.3 USB-TO-USB OR USB-TO-ETHERNET BRIDGE THROUGH ETHERNET REPEATER CONTROLLER............................ 28 A.4 USB-TO-USB OR USB-TO-ETHERNET BRIDGE THROUGH ETHERNET SWITCH CONTROLLER................................. 28 DEMONSTRATION CIRCUIT A: AX88170 + ETHERNET PHY.............................................................................................29 DEMONSTRATION CIRCUIT B: AX88170 + HOMEPNA 1M8 PHY ....................................................................................31 DEMONSTRATION CIRCUIT C: 4 USB PORTS + 1 ETHERNET PORT BRIDGE AP.....................................................33 2 ASIX ELECTRONICS CORPORATION
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AX88170
PRELIMINARY
FIGURES
FIG - 1 AX88170 BLOCK DIAGRAM ..................................................................................................................................................... 4 FIG - 2 AX88170 PIN CONNECTION DIAGRAM WITH MII INTERFACE ......................................................................................... 5 FIG - 3 AX88170 PIN CONNECTION DIAGRAM RMII INTERFACE .................................................................................................. 6
TABLES
TAB - 1 USB BUS INTERFACE SIGNALS GROUP .................................................................................................................................. 7 TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP ......................................................................................................................... 7 TAB - 3 MII INTERFACE SIGNALS GROUP (MAC MODE) ................................................................................................................. 8 TAB - 4 MII INTERFACE SIGNALS GROUP (PHY MODE) ................................................................................................................... 8 TAB - 5 RMII INTERFACE SIGNAL PINS (PHY MODE)....................................................................................................................... 9 TAB - 6 MISCELLANEOUS PINS GROUP ............................................................................................................................................. 10 TAB - 7 EEPROM MEMORY MAPPING............................................................................................................................................. 11
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1.0 Introduction
1.1 General Description:
The AX88170 USB to Fast Ethernet Controller is a high performance and highly integrated USB busEthernet Controller with embedded 5K*16 bit SRAM. The AX88170 contains a full speed USB interface to host CPU and compliant with USB Communication Class Spec. 1.0. The AX88170 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII) interface to simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional MII/RMII interface with PHY mode, combines with Ethernet repeater or switch IC can build a multiple ports USB-to-USB bridge application. AX88170 uses 64-pin LQFP low profile package, 48MHz operation for USB and 25MHz operation for Ethernet, CMOS process with pure 3.3V operation and 5 Volt I/O tolerance.
1.2 AX88170 Block Diagram:
SMDC SMDIO STA 5K* 16 SRAM Memory Arbiter
EECS EECK EEDI EEDO
SEEPROM Loader I/F
USB to Ethernet Bridge
MAC Core MII I/F Or RMII I/F
USB Core and Interface
D-/D+ Fig - 1 AX88170 Block Diagram
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AX88170
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1.3 AX88170 Pin Connection Diagram with MII Interface
The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig - 2 AX88170 Pin Connection
Diagram.
VSS VDD 48M_XOUT 48M_XIN VSS VDD TEST0 TEST1 TEST2 TEST3 VDD TEST_OUT TEST4 LD_RDY ACT/LINK VSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
EEDO EEDI EECK EECS VDD /S_RMII VSS /HomeLink GPIO1 /PHY_RST GPIO0 VDD 25M_XOUT 25M_XIN VSS 25M_CLKO
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
ASIX AX88170 (MII Interface)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
RX_DV RX_ER VDD RXD3 RXD2 RXD1 RXD0 VSS RX_CLK VDD TX_EN TXD3 TXD2 TXD1 TXD0 VSS
Fig - 2 AX88170 Pin Connection Diagram with MII Interface
D+ DVDD /RST VSS SPD_UP S_EXT /S_FDPX /S_MAC VDD VSS MDC COL MDIO CRS TX_CLK
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AX88170
PRELIMINARY
1.4 AX88170 Pin Connection Diagram with RMII Interface
The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig - 3 AX88170 Pin Connection
Diagram RMII Interface.
VSS VDD 48M_XOUT 48M_XIN VSS VDD TEST0 TEST1 TEST2 TEST3 VDD TEST_OUT TEST4 LD_RDY ACT/LINK VSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
EEDO EEDI EECK EECS VDD /S_RMII VSS /HomeLink GPIO1 /PHY_RST GPIO0 VDD 25M_XOUT 25M_XIN VSS 25M_CLKO
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
ASIX AX88170 (RMII Interface)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
NC NC VDD NC NC RXD1 RXD0 VSS NC VDD TX_EN NC NC TXD1 TXD0 VSS
Fig - 3 AX88170 Pin Connection Diagram RMII Interface
D+ DVDD /RST VSS SPD_UP S_EXT /S_FDPX /S_MAC VDD VSS MDC COL MDIO CRS_DV REF_CLK
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AX88170
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2.0 Signal Description
The following terms describe the AX88170 pin-out: All pin names with the "/" suffix are asserted low. The following abbreviations are used in following Tables.
I O I/O OD
Input Output Input/Output Open Drain
PU PD P
Pull Up Pull Down Power Pin
2.1 USB Bus Interface Signals Group
SIGNAL D+ DTYPE I/O I/O PIN NO. 1 2 DESCRIPTION USB Data Plus Pin USB Data Minus Pin
Tab - 1 USB bus interface signals group
2.2 EEPROM Signals Group
SIGNAL EECS EECK EEDI EEDO TYPE O O O I/PU PIN NO. 45 46 47 48 DESCRIPTION EEPROM Chip Select : EEPROM chip select signal. EEPROM Clock : Signal connected to EEPROM clock pin. EEPROM Data In : Signal connected to EEPROM data input pin. EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab - 2 EEPROM bus interface signals group
2.3a MII interface signals group (MAC mode)
When /S_RMII=1 and /S_MAC=0 SIGNAL TYPE PIN NO. RXD[3:0] I/PU 29, 28 27, 26 CRS I/PD 15 RX_DV I/PD 32 DESCRIPTION Receive Data: RXD[3:0] is driven by the PHY synchronously with respect to RX_CLK. Carrier Sense: Asynchronous signal CRS is asserted by the PHY when either the transmit or receive medium is non-idle. Receive Data Valid: RX_DV is driven by the PHY synchronously with respect to RX_CLK. Asserted high when valid data is present on RXD [3:0]. Receive Error: RX_ER is driven by PHY and synchronous to RX_CLK, is asserted for one or more RX_CLK periods to indicate to the port that an error has detected. Receive Clock: RX_CLK is a continuous clock that provides the timing reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from the PHY to the MII port of the MAC. Collision: this signal is driven by PHY when collision is detected. Transmit Enable: TX_EN is transition synchronously with respect to the rising edge of TX_CLK. TX_EN indicates that the port is presenting 7 ASIX ELECTRONICS CORPORATION
RX_ER
I/PD
31
RX_CLK
I/PU
24
COL TX_EN
I/PD O
13 22
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AX88170
SIGNAL TXD[3:0] TYPE O PIN NO. 21, 20 19, 18 16
PRELIMINARY
DESCRIPTION nibbles on TXD [3:0] for transmission. Transmit Data: TXD[3:0] is transition synchronously with respect to the rising edge of TX_CLK. For each TX_CLK period in which TX_EN is asserted ,TXD[3:0] are accepted for transmission by the PHY. Transmit Clock: TX_CLK is a continuous clock from PHY. It provides the timing reference for the transfer of the TX_EN and TXD[3:0] signals from the MII port to the PHY. Station Management Data Clock: The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. MDC is a 2.5MHz frequency clock output. Station Management Data Input/Output: Serial data input/output transfers from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII specification.
TX_CLK
I
MDC
O
12
MDIO
I/O/PU
14
Tab - 3 MII interface signals group (MAC mode)
2.3b MII interface signals group (PHY mode)
When /S_RMII=1 and /S_MAC=1 SIGNAL TYPE PIN NO. RXD[3:0] O 29, 28 27, 26 CRS O 15 RX_DV RX_ER RX_CLK COL TX_EN TXD[3:0] TX_CLK O O O O I/PD I/PU O 32 31 24 13 22 21, 20 19, 18 16 DESCRIPTION Receive Data: Basically RXD[3:0] is transformed from TXD[3:0] of MAC mode of MII interface. Carrier Sense: Basically CRS is transformed from TX_EN of MAC mode of MII interface. Receive Data Valid: Basically RX_DV is transformed from TX_EN of MAC mode of MII interface. Receive Error: No used Receive Clock: Basically RX_CLK is sourced from internal 25MHz local clock. Collision: this signal is generated by internal logic when collision is detected. Transmit Enable: Basically TX_EN is simulation from RX_DV of MAC mode of MII interface. Transmit Data: Basically TXD[3:0] is simulation from RXD[3:0] of MAC mode of MII interface. Transmit Clock: Basically TX_CLK is sourced from internal 25MHz local clock.
Tab - 4 MII interface signals group (PHY mode)
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2.4 RMII interface signal pins (PHY mode)
When /S_RMII=0 and /S_MAC=1 SIGNAL TYPE PIN NO. RXD[1:0] O 27, 26 CRS_DV TXD[1:0] TX_EN REF_CLK O I/PU I/PD I 15 19, 18 22 16
PRELIMINARY
DESCRIPTION Receive Data : Basically RXD[1:0] is transformed from TXD[1:0] of MAC mode of RMII interface. Carrier Sense _ Data Valid : Basically CRS_DV is transformed of TX_EN from MAC mode of RMII interface. Transmit Data : Basically TXD[1:0] is transformed from RXD[1:0] of MAC mode of RMII interface. Transmit Enable : Basically TX_EN is transformed from RX_DV from MAC mode of RMII interface. Reference clock : The input is a continue clock at 50Mhz for timing reference with RMII interface.
Tab - 5 RMII interface signal pins (PHY mode)
2.5 Miscellaneous pins group
SIGNAL 25M_XIN TYPE I PIN NO. 35 DESCRIPTION CMOS Local Clock : Typical a 25Mhz clock, +/- 100 ppm, 40%-60% duty cycle. ( See application note also ) Crystal Oscillator Input : Typical a 25Mhz crystal, +/- 25 ppm can be connected across 25M_XIN and 25M_XOUT. Crystal Oscillator Output : Typical a 25Mhz crystal, +/- 25 ppm can be connected across 25M_XIN and 25M_XOUT. If a single-ended external clock is connected to 25M_XIN, the crystal output pin should be left floating. 48Mhz CMOS Clock In : Typical a 48Mhz clock, +/- 500 ppm, 40%-60% duty cycle. ( See application note also ) 48Mhz Crystal Oscillator Input: Typical a 48Mhz crystal, +/- 100 ppm can be connected across 48M_XIN and 48M_XOUT. 48Mhz Crystal Oscillator Output: Typical a 48Mhz crystal, +/- 100 ppm can be connected across 48M_XIN and 48M_XOUT. If a single-ended external clock is connected to 48M_XIN, the crystal output pin should be left floating. Clock Output : This clock is source from 25M_XIN. Reset: Reset is active low then place AX88170 into reset mode immediately. During Rising edge the AX88170 loads the EEPROM data. Set to RMII mode: 0: RMII mode is selected. 1: MII mode is selected. (default) Set MII/RMII interface to MAC mode: 0: MAC mode is selected. (default) 1: PHY mode is selected. Set duplex mode when PHY mode is selected or When S_EXT is set and MAC mode is selected: 0: full-duplex mode is selected. (default) 1: half-duplex mode is selected. Select where duplex mode is sourced from when MAC mode: 0: duplex mode depands on internal register. (default) 1: duplex mode depands on external signal /S_FDPX The setting is enable speed up test mode: 9 ASIX ELECTRONICS CORPORATION
25M_XOUT
O
36
48M_XIN
I
52
48M_XOUT
O
51
25M_CLKO /RST
O I/PD
33 4
/S_RMII
I/PU
43
/S_MAC
I/PD
9
/S_FDPX
I/PD
8
S_EXT
I/PD
7
SPD_UP
ID
6
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AX88170
TEST0 TEST1 TEST2 TEST3 TEST4 TEST_OUT LDRDY ACT/LINK I/PD I/PD I I/PD I/PD O O O
PRELIMINARY
0: Normal operation mode. 1: Speed up test mode enable. 55 Test Pin: This pin for test purpose only. Pull down the pin or keep no connection for normal operation. 56 Test Pin: This pin for test purpose only. Pull down the pin or keep no connection for normal operation. 57 Test Pin: This pin for test purpose only. Pull down the pin for normal operation. 58 Test Pin: This pin for test purpose only. Pull down the pin or keep no connection for normal operation. 61 Test Pin: This pin for test purpose only. Pull down the pin or keep no connection for normal operation. 60 Test Output Pin: This pin for test purpose only. 62 Load EEPROM data completed indicator. Active high. 63 LED indicator: When link fail, drives logic high always. When link OK, the pin drives logic low and will drives high a period when line has activity (data transfer). 39 PHY Reset: This pin is used to reset PHY and is an active low signal. 38 General Purpose I/O 0: Refer to section 4.3 USB Vendor Commands 40 General Purpose I/O 1: Refer to section 4.3 USB Vendor Commands 41 Link Status: For external HomePHY link state input active low 3, 10, 23, 30 Power Supply: +3.3V DC. 37, 44, 50 54,59 5, 11 Power Supply: +0V DC or Ground Power. 17, 25, 34 42, 49, 53 64
/PHY_RST GPIO0 GPIO1 /HOMELINK VDD
O B/PD B/PD I/PU P
VSS
P
Tab - 6 Miscellaneous pins group
MII/RMII interface Cross Reference Table
MII RXD[0] RXD[1] RXD[2] RXD[3] CRS RX_DV RX_CLK RX_ER TX_EN TX_CLK TXD[0] TXD[1] TXD[2] TXD[3] COL RXD[0] RXD[1] RMII
CRS_DV
TX_EN REF_CLK (50MHz) TXD[0] TXD[1]
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3.0 EEPROM Memory Mapping
EEPROM OFFSET 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H-18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H-4FH 50H-FFH HIGH BYTE RESERVED *FLAG EEPROM OFFSET OF DEVICE DESCRIPTOR LENGTH OF CONFIGURATION DESCRIPTOR EEPROM OFFSET OF CONFIGURATION (BYTE) DESCRIPTOR NODE ID 1 NODE ID 0 NODE ID 3 NODE ID 2 NODE ID 5 NODE ID 4 LANGUAGE ID HIGH BYTE LANGUAGE ID LOW BYTE LENGTH OF STRING INDEX 1 EEPROM OFFSET OF STRING INDEX 1 LENGTH OF STRING INDEX 2 EEPROM OFFSET OF STRING INDEX 2 LENGTH OF STRING INDEX 3 EEPROM OFFSET OF STRING INDEX 3 LENGTH OF STRING INDEX 4 EEPROM OFFSET OF STRING INDEX 4 LENGTH OF STRING INDEX 5 EEPROM OFFSET OF STRING INDEX 5 LENGTH OF STRING INDEX 6 EEPROM OFFSET OF STRING INDEX 6 LENGTH OF STRING INDEX 7 EEPROM OFFSET OF STRING INDEX 7 LENGTH OF STRING INDEX 8 EEPROM OFFSET OF STRING INDEX 8 (19H) MAX PACKETSIZE HIGH BYTE MAX PACKET LOW BYTE HOMEPNA PHY ID ETHERNET PHY ID PAUSE PACKET HIGH WATER LEVEL PAUSE PACKET LOW WATER LEVEL RESERVED 03H 0CH BYTE 2 OF UNICODE MAC ADDRESS **BYTE 1 OF UNICODE MAC ADDRESS BYTE 4 OF UNICODE MAC ADDRESS BYTE 3 OF UNICODE MAC ADDRESS BYTE 6 OF UNICODE MAC ADDRESS BYTE 5 OF UNICODE MAC ADDRESS BYTE 8 OF UNICODE MAC ADDRESS BYTE 7 OF UNICODE MAC ADDRESS BYTE 10 OF UNICODE MAC ADDRESS BYTE 9 OF UNICODE MAC ADDRESS BYTE 12 OF UNICODE MAC ADDRESS BYTE 11 OF UNICODE MAC ADDRESS DEVICE /CONFIGURATION /INTERFACE /ENDPOINT DESCRIPTOR STRINGS LENGTH OF DEVICE DESCRIPTOR (BYTE) LOW BYTE WORD COUNT FOR PRELOAD
Tab - 7 EEPROM Memory Mapping Note: *Flag: Bit 0 e Self Powered (for USB GetStatus) Bit 1 e Bus Powered (Reserved) Bit 2 e Remote Wakeup (for USB GetStatus) Bit 3 e Interrupt Endpoint Enaable (Reserved) Bit 4 e ClkNoStop (for Self Power only) Bit 5 e Reserved Bit 6 e Reserved Bit 7 e Reserved Bit 8 e Capture Effective Mode Bit 9 e Flow Control selector (1: software, o: read from PHY) Bit A - F e Reserved
Bit 4 also effect LED display, if high then LED display USB active only otherwise display USB link and activity. (In Self power mode Bit_4 set to high) **Unicode MAC Address: If the MAC's NODE ID is 01,23,45,67,89,ABh respect to NODE ID 0, NODE ID 1, ... NODE ID5 Then the unicode will be 30-31,32-33,34-35,36-37,38-39,41-42h respects to BYTE 1 OF UNICODE MAC ADDRESS- BYTE 2 OF UNICODE MAC ADDRESS, ... -BYTE 12 OF UNICODE MAC ADDRESS. 11 ASIX ELECTRONICS CORPORATION
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4.0 USB Commands
There are three command groups for Endpoint 0 in AX88170: l The USB standard commands l USB Communication Class commands l USB vendor commands.
4.1 USB standard commands
** The Language ID is 0x0904 for English ** PPLL means buffer length ** CC means configuration number ** I I means Interface number SETUP COMMAND 80 06 00 01 00 00 LL PP 80 06 00 02 00 00 LL PP 80 06 00 03 00 00 LL PP 80 06 01 03 09 04 LL PP 80 06 02 03 09 04 LL PP 80 06 03 03 09 04 LL PP 80 06 04 03 09 04 LL PP 80 06 05 03 09 04 LL PP 80 06 06 03 09 04 LL PP 80 06 07 03 09 04 LL PP 80 06 08 03 09 04 LL PP 80 08 00 00 00 00 01 00 00 09 CC 00 00 00 00 00 81 0A 00 00 I I 00 01 00 01 0B AS 00 01 00 00 00 DATA IN/OUT Data PPLL bytes Data PPLL bytes Data 2 bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data 12 bytes Data 1 bytes No Data Data 1 byte No Data DESCRIPTION Get Device Descriptor Get Configuration Descriptor Get Supported Language ID Get Manufacture String Get Product String Get Serial Number String Get Configuration String Get Interface 0 String Get Interface 1/0 String Get Interface 1/1 Stirng Get Ethernet Address String Get Configuration Set Configuration Get Interface Set Interface
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AX88170 4.2 USB Communication Class Commands
** NN: number of multicast addresses ** BBAA: Ethernet Packet Filter ** TTSS: Number of Ethernet Statics SETUP COMMAND 21 40 NN 00 00 00 6*N 00 21 41 00 00 00 00 10 00 A1 42 00 00 00 00 02 00 21 43 AA BB 00 00 00 00 DATA IN/OUT Data 6*N bytes Data 16 bytes Data 2 bytes No Data
PRELIMINARY
DESCRIPTION Set Ethernet Multicast Filters Set Ethernet Power Management Pattern Get Ethernet Power Management Pattern Set Ethernet Packet Filter (AA BB)
Description of Ethernet Packet Filter (AA BB) Bitmap
BB = [D15:D8] AA = [D7:D0] Bit position D15..D5 D4
D3
D2
D1
D0
DESCRIPTION RESERVED (Reset to Zero) PACKET_TYPE_MULTICAST 1: All multicast packets enumerated in the device's multicast address list are forwarded up to the host. 0: Disabled. PACKET_TYPE_BROADCAST 1: All broadcast packet packets received by the networking device are forwarded up to the host. 0: Disable. PACKET_TYPE_DIRECTED 1: Directed packets received containing a destination address equal to the MAC address of the networking device are forwarded up to the host. 0: Always not set to Zero. PACKET_TYPE_ALL_MULTICAST 1 : ALL multicast frames received by the networking device are forwarded up to the host, not just the ones enumerated in the device's multicast address list. 0: Disabled. PACKET_TYPE_PROMISCUOUS 1: ALL frames received by the networking device are forwarded up to the host. 0: Disabled.
Tab - 9 Ethernet Packet Filter Bitmap
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AX88170 4.3 USB Vendor Commands
SETUP COMMAND C0 02 XX YY 00 0M 02 00 40 03 XX YY PP QQ 00 00 40 04 XX YY PP QQ 00 00 40 06 00 00 00 00 00 00 C0 07 PI 00 RG 00 02 00 40 08 PI 00 RG 00 02 00 C0 09 00 00 00 00 01 00 40 0A 00 00 00 00 00 00 C0 0B DR 00 00 00 02 00 40 0C DR 00 MM SS 00 00 40 0D 00 00 00 00 00 00 40 0E 00 00 00 00 00 00 C0 0F 00 00 00 00 02 00 40 10 RR 00 00 00 00 00 C0 11 00 00 00 00 03 00 40 12 II 00 00 00 00 00 40 13 II 00 00 00 00 00 40 14 II 00 00 00 00 00 C0 15 00 00 00 00 08 00 40 16 00 00 00 00 08 00 C0 17 00 00 00 00 06 00 C0 19 00 00 00 00 02 00 C0 1A 00 00 00 00 01 00 40 1B MM 00 00 00 00 00 C0 1C 00 00 00 00 01 00 40 1D MM 00 00 00 00 00 Notes: * Read / Write Medium status Bit7 Bit6 Read GPI1 X Write GPO1 GPO1EN DATA IN/OUT Data 2 bytes No Data No Data No Data Data 2 Bytes Data 2 Bytes Data 1 Bytes No Data Data 2 Bytes No Data No Data No Data Data 2 Bytes No Data Data 3 Bytes No Data No Data No Data Data 8 Bytes Data 8 Bytes Data 6 Bytes Data 2 Bytes Data 1 Byte No Data Data 1 Byte No Data
PRELIMINARY
DESCRIPTION Read Rx/Tx SRAM M = 0 : Rx, M=1 : Tx Write Rx SRAM Write Tx SRAM Disable H/W MII Operation Read MII Register Write MII Register Read MII Operation Mode Enable H/W MII Operation Read SROM Write SROM Write SROM Enable Write SROM Disable Read Rx Control Register Write Rx Control Register Read IPG/IPG1/IPG2 Register Write IPG Register Write IPG1 Register Write IPG2 Register Read Multi-Filter Array Write Multi-Filter Array Read Node ID Read Ethernet/HomePNA PhyID Read Medium Status(*) Write Medium Mode(*) Get Monitor Mode Status(**) Set Monitor Mode On/Off(**)
Bit5 GPI0 GPO0
Bit4 X GPO0EN
Bit3 Bit2 Home_Link 100MHz FRBI 100MHz
Bit1 Bit0 Full_Duplex Link Full_Duplex Link
** Read / Write Monitor Mode Bit7-5 Bit4 Bit3 Read Reserved Flow_Contron_En X (Hardware_Version for ASIX only) Write X Flow_Contron_En X
Bit2 Bit1 Bit0 Magic_Packet_En Link_UP_Wake Monitor_Mode
Magic_Packet_En Link_UP_Wake Monitor_Mode
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Interrupt Endpoint report link status format Byte Number Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
PRELIMINARY
A1 00 NN 00 NN NN NN 00
Fixed value Fixed value Bit_0 : Ethernet Link state, Bit_1 : Home PHY Link state (active high) Fixed value Bit_0 : 100MHz speed detect Reserved (Hardware version for ASIX only) Bit_0 : Full Duplex Fixed value
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5.0 USB Configuration Structure
5.1 USB Configuration.
The AX88170 supports 1 Configuration only.
5.2 USB Interface Class.
The AX88170 supports 2 interfaces, the interface 0 is Data Interface and interface 1 is for Communication Interface.
5.3 USB Endpoints.
The AX88170 supports 4 endpoints. Endpoint 0 e Control endpoint, it is for configuring device. Endpoint 1 e (optional) Interrupt endpoint, it is for reporting status change Endpoint 2e Bulk Out endpoint, it is for Transmitting Ethernet Packet. Endpoint 3 e Bulk In endpoint, it is for Receiving Ethernet Packet.
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AX88170
PRELIMINARY
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description SYM Min Max Units Operating Temperature Ta 0 +85 C Storage Temperature Ts -55 +150 C Supply Voltage Vdd -0.3 +3.6 V Input Voltage Vin -0.3 Vdd+0.3 V Output Voltage Vout -0.3 Vdd+0.3 V Lead Temperature (soldering 10 seconds maximum) Tl -55 +240 C Note: Stress above those listed under Absolute M aximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
6.2 General Operation Conditions
Description Operating Temperature Supply Voltage SYM Min Ta 0 Vdd +3.0 Tpy 25 +3.30 Max +70 +3.6 Units C V
6.3 DC Characteristics
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0C to 70C) Description Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Input Leakage Current Output Leakage Current Input Pull-up / down resistance Description Power Consumption (3.3V) SYM Vil Vih Vol Voh Iil Iol Ri SYM SPt3v Min 0.7*Vdd 2.4 -1 -10 75 Min 40 Tpy Max Tpy Max 0.3*Vdd 0.4 +1 +10 Units V V V V uA uA K ohm Units mA
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4 A.C. Timing Characteristics
6.4.1 25M_XIN
Thigh 25M_XIN
Tr
Tf Tcyc
Tlow
25M_CLKO
Tod
Symbol
Tcyc Thigh Tlow Tr/Tf Tod
Description
CYCLE TIME CLK HIGH TIME CLK LOW TIME CLK SLEW RATE LCLK/XTALIN TO 25M_CLKO OUT DELAY
Min 16 16 1 8
Typ. 40 20 20 -
Max 24 24 4 29
Units ns ns ns ns ns
6.4.2 48M_XIN
Thigh 48M_XIN
Tr
Tf Tcyc
Tlow
Symbol
Tcyc Thigh Tlow Tr/Tf CYCLE TIME CLK HIGH TIME CLK LOW TIME CLK SLEW RATE
Description
Min 8.3 8.3 1
Typ. 20.83 10.42 10.42 -
Max 12.5 12.5 4
Units ns ns ns ns
6.4.3 Reset Timing
25M_XIN /RST
Symbol
Trst Reset pulse width
Description
Min 100
Typ. -
Max -
Units 25M _XIN
18
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
19
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
6.4.4 MII Timing of MAC mode
Ttclk Ttch Ttcl
PRELIMINARY
TXCLK(in) Ttv TXD<3:0>(out) Tth
TXEN(out) Trclk Trch Trcl
RXCLK(in) Trs RXD<3:0>(in) Trh
RXDV(in) Trs1 RXER(in)
CRS(in)
Symbol
Ttclk Ttclk Ttch Ttch Trch Trch Ttv Tth Trclk Trclk Trch Trch Trcl Trcl Trs Trh Trs1
Description
Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) Clock to data valid Data output hold time Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) data setup time data hold time RXER data setup time
Min 14 140 14 140 5 14 140 14 140 6 10 10
Typ. 40 400 40 400 -
Max 26 260 26 260 20 26 260 26 260 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
6.4.5 MII Timing of PHY mode
Ttclk Ttch Ttcl
PRELIMINARY
TXCLK(out) Tts TXD<3:0>(in) Tth
TXEN(in) Trclk Trch Trcl
RXCLK(out) Trs RXD<3:0>(out) Trh
RXDV(out) Tcrsh CRS(out)
Symbol
Ttclk Ttclk Ttch Ttch Trch Trch Tts Tth Trclk Trclk Trch Trch Trcl Trcl Trv Trh Tcrsh
Description
Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) TXD, TXEN setup to TXCLK high TXD, TXEN hold to TXCLK high Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) RXD, RXDV valid to RXCLK high RXCLK high to RXD, RXDV invalid RXCLK high to CRS invalid
Min 14 140 14 140 15 0 14 140 14 140 10 10 10
Typ. 40 400 40 400 -
Max 26 260 26 260 26 260 26 260 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
6.4.6 RMII Interface Timing of PHY Mode Tclk REF_CLK Ts TX_EN (in) Th Tch Tcl
PRELIMINARY
TXD
(in)
CRS_DV (out) Tod RXD (out) Tod
Symbol Tclk Tch Tcl Ts Th Tod
Description REF_CLK Clock Cycle Time REF_CLK Clock High Time REF_CLK Clock Low Time TXEN and TXD data setup to REF_CLK high TXEN and TXD data hold from REF_CLK high REF_CLK rising edge to CRS_DV, RXD delay
Min 19.998 7 7 4 2 4
Typ. 20 10 10
Max 20.002 13 13
Units ns ns ns ns ns ns
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4.7 STATION MANAGEMENT TIMING
Tclk
MDC
Tch Tcl Tod
MDIO (output)
Ts
Th
MDIO (input)
Symbol Tclk Tch Tcl Tod Ts Th
Description MDC Clock Cycle Time MDC Clock High Time MDC Clock Low Time Clock Falling Edge to Output Valid Delay Data In Setup Time Data In Hold Time
Min
Typ. 2560 1280 1280
Max
2 10 100
9
Units ns ns ns ns ns ns
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
6.4.8 SERIAL EEPROM TIMING
Tclk
EECK
Tch Tdv Tcl Tod VALID
EEDI (output)
VALID Tsc s
Thcs
Tlcs
EECS
Ts Th
EEDO (input)
DATA VA LID
Symbol Tclk Tch Tcl Tdv Tod Tscs Thcs Tlcs Ts Th
Description EECK Clock Cycle Time EECK Clock High Time EECK Clock Low Time EEDI Data Valid Output to EECK High Time EECK High to EEDI Data Output Delay Time EECS Valid to EECK High Time EECK Low to EECS Invalid Time Minimum EECS Low Time Data Input Setup Time Data Input Hold Time
Min 2500 2500 500 500 300 0 2500 10 100
Typ. 5120
Max 9 9
Units ns ns ns ns ns ns ns ns ns ns
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
7.0 Package Information
He E A A2 A1
Hd
D
pin 1
b
e
25
ASIX ELECTRONICS CORPORATION
L
L1
CONFIDENTIAL
AX88170
SYMBOL MIN.
A1 A2 A b D E e Hd He L L1 0 0.45 0.17 0.22 10.00 10.00 0.5 12.00 12.00 0.60 1.00 3.5 0.05 1.35
PRELIMINARY
MILIMETER NOM
0.1 1.40
MAX
0.15 1.45 1.60 0.27
0.75
7
Appendix A: System Applications
Some typical applications for AX88170 are illustrated bellow.
A.1 USB to Fast Ethernet Converter
RJ45
MAGNETIC
10/100 PHY/TxRx
AX88170
USB I/F
EEPROM
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
A.2 USB to Fast Ethernet and/or HomeLAN Combo solution
RJ45 RJ11
PRELIMINARY
MAGNETIC
MAGNETIC
10/100 Mbps Ethernet PHY/TxRx
1/10 Mbps Home LAN PHY
AX88170
USB I/F
EEPROM
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ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88170
PRELIMINARY
A.3 USB-to-USB or USB-to-Ethernet Bridge through Ethernet Repeater Controller
AX88875
Repeater Controller
MII I/F MII I/F MII I/F MII I/F MII I/F
AX88170
AX88170
AX88170
AX88170
Ethernet PHY for Up-link
USB I/F
USB I/F
USB I/F
USB I/F
Client PC A
Client PC B
Client PC C
Client PC D
To Ethernet Backend
Note : Using AX88871 for 8-port or less then 8-port solutions.
A.4 USB-to-USB or USB-to-Ethernet Bridge through Ethernet Switch Controller
AX88615
Switch Controller
MII I/F MII I/F MII I/F MII I/F MII I/F
AX88170
AX88170
AX88170
AX88170
Ethernet PHY for Up-link
USB I/F
USB I/F
USB I/F
USB I/F
Client PC A
Client PC B
Client PC C
Client PC D
To Ethernet Backend
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ASIX ELECTRONICS CORPORATION
AX88170
AX88710 L Application for 10BASE-T/100BASE-TX
4 M XN 8 _I L 1 2.2uH
USB to Fast Ethernet/HomePNA Controller
R1 2K 0 R2 1 M
Demonstration Circuit A: AX88170 + Ethernet PHY
Y1 R3 4MX U 8 _OT 2 M XN 5 _I 4M 8 C1 8 p C2 8 p 0 2M 5 C3 2P 0 C4 2P 0 Y2 2MX U 5 _OT
C5 2p 2 VDD3
*1 USB Port Link/Act LED
VDD3 R4 30 3 D1 LD E RST# 4 4MX U 8 _OT 4 M XN 8 _I ACT/LINK# 5 1 5 2 6 3
U1 4MX U 8 _OT 4 M XN 8 _I ACT/LINK /HOMELINK GPIO1 /PHY_RST GPIO0 RX_DV R_R XE RD X3 RD X2 RD X1 RD X0 R_L XCK T_N XE TD X3 TD X2 TD X1 TD X0 TX_CLK CRS CL O MDIO MC D 2MCK 5 _LO 2 M XN 5 _I 2MX U 5 _OT ED EO ED EI EC EK EC ES /S_RMII /S_MAC /_DX SF P SE T _X S DU P_P 4 1 4 0 3 9 3 8 3 2 3 1 2 9 2 8 2 7 2 6 2 4 2 2 2 1 2 0 1 9 1 8 1 6 1 5 1 3 1 4 1 2 3 3 3 5 3 6 4 8 4 7 4 6 4 5 4 3 9 8 7 6 PRST# PRST# RD XV RE XR RD X3 RD X2 RD X1 RD X0 RXCLK TE XN TD X3 TD X2 TD X1 TD X0 T CK XL CRS CL O MDIO MC D 25MHZ
J1 S
U BC N S-O
R5 1.5K 4 3 2 1 R6 R7 1 8 1 8 D+ D6 2 1 2 5 5 5 6 5 7 5 8 6 1 6 0 VDD3 U2 VDD3 VC C RST EE# GD N V30 60C C9 VDD3 0.1u C10 0.1u C11 0.1u C12 0.1u C13 0.1u 5 1 1 1 7 2 5 3 4 4 2 4 9 5 3 6 4 1 2 3 VDD3 RST# GD N VDD3 VDD3 VDD3 3 1 0 2 3 3 0 3 7 4 4 5 0 5 4 5 9
/RST
DD+ VDD5 GD N
LED ERY D+ DTS0 ET TS1 ET TS2 ET /EP78DIS TEST3 TS4 ET TS_ U E TO T VD D VD D VD D VD D VD D VD D VD D VD D VD D
C6 S 2P 0
C7 2P 0
R8
4.7K
RD XV RE XR RD X3 RD X2 RD X1 RD X0 RXCLK TE XN TD X3 TD X2 TD X1 TD X0 T CK XL CRS CL O MDIO MC D 25MHZ 2 M XN 5 _I 2MX U 5 _OT ED EO ED EI EC EK EC ES
4 2
3 1
C8 0.01u
L 2 FS UE
L 3 F.B.
L 4 F.B. D2 1N4148 RST# R9 1K 0
VS S VS S VS S VS S VS S VS S VS S VS S VS S
*2 RC reset (option)
C14 0.47u
A 8 1 0L X87 EC ES EC EK ED EI ED EO 1 2 3 4
U3 CS S K DI DO 93C56R VC C NC NC GD N 8 7 6 5 VDD3
VDD3 5 V U4 3 VOUT VIN ADJ/GND + C16 10u/16V C19 1000P AMS1117 - 3.3 10u/16V 2 1 + C15 C17 0.1u C18 0.01u GD N GD N VDD3 VDD3
ASIX ELECTRONIC CORPORATION Title A 810 X87 Size B Date: Document Number 170AP1A.SCH Monday, February 26, 2001 Sheet 1 o f 2 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
Set PHY Address to 00010G
U5 RXDV RXER RXD3 RXD2 RXD1 RXD0 RXCLK TXEN TXD3 TXD2 TXD1 TXD0 TXCLK 18 19 20 21 22 23 24 27 29 30 31 32 33 28 RXDV RXER RXD3 RXD2 RXD1 RXD0 RXCLK TXEN TXD3 TXD2 TXD1 TXD0 TXCLK TXER
USB to Fast Ethernet/HomePNA Controller
R10 49.9 53 54 61 62 4 2 11 17 43 44 40 42 41 50 49 8 1 5 TDP TDN RDP RDN R12 R13 R14 R15 R23 R24 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K VDD3 R11 49.9 U6 TPTX+ TPTXTPRX+ TPRXAUTONEN 100FDEN 100HDEN LEDSP/10FDEN LEDFD/10HDEN LNKLED/BPALIGN LEDRX LEDCOL/BP4B5B LEDTX/ACTLED/BPSCR REF100 REF10 RESV RESV TPTXTR 1 2 3 6 7 8 1 2 3 6 7 8 TS6121A R16 49.9 R17 49.9 C20 0.01u ACTLED R26 R27 R28 GND GND GND 4.7K C23 301 4.65K 0.01u C24 0.01u C21 0.01u R18 75 R19 75 R20 75 R21 75 16 15 14 11 10 9 16 15 14 11 10 9 TX+ TXRX+ RX-
TX RX
1:1 1:1
J2 1 2 3 6 4 5 7 8 RJ45 S S
GND
R22
4.7K
SPDLED FULLED LNKLED
CRS COL MDIO MDC PRST# 25MHZ
34 39 VDD3 R25 2K 35 45 9 GND 47 48 16 12 10 7 13 15 25 37 38 46
CRS/PHY[3] COL/PHY[4] MDIO MDC RSTZ XIN XOUT MDIOINTZ/PHY[2] PHY[1] PHY[0] EQVDD1 VDD5 VDD1 VDD8 VDD4 VDD6 XTLVDD
C22 0.01u/2KV
VDD3 R30 GND R31
4.7K 4.7K VDD3 VDD3 VDD3 VDD3 VDD3
CSVDD CSVDD
58 57 C27 56 0.1u + C25 4.7u/16V
R29
1
VDD3 VDD3 C26 1000P FULLED R32 510 LED D3 FULL DUPLEX LED
CSGND
L5 TXVDD1 TXVDD2 51 55 C30 52 0.1u C31 0.1u + C28 F.B. VDD3 SPDLED C29 1000P ACTLED L6 59 64 C39 60 63 0.1u C40 0.1u + C37 F.B. VDD3 LNKLED C38 1000P R35 510 D6 LED LINK LED R34 510 D5 LED ACTIVITY LED R33 510 LED D4 SPEED LED
TXGND1 C32 0.1u C33 0.1u C34 C35 C36 0.1u 3 6 14 26 36 GND9 EQGND1 GND1 GND8 GND4 LU3X31T-T64 RXVDD1 RXVDD2 RXGND1 RXGND2
4.7u/16V
0.1u 0.1u
4.7u/16V
VDD3 VDD3 + C41 4.7u/16V GND VDD3
C42 0.1u GND
ASIX ELECTRONIC CORPORATION Title LU3X31 Size B Date: Document Number 170AP1A1.SCH Monday, February 26, 2001 Sheet 2 of 2 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
Demonstration Circuit B: AX88170 + HomePNA 1M8 PHY
AX88710 Application for 1M8 HomePNA
R18 20k R19 1M Y1 48M_XIN 48M L3 2.2uH C15 8p C16 8p 0 C17 20P R20 48M_XOUT 25M_XIN 25M C18 20P Y2 25M_XOUT
C19 22pF U3 48M_XOUT 48M_XIN ACT/LINK# D5 LED RST# J2 S USB-CON R22 1.5K 4 3 2 1 R24 R25 18 18 D+ D62 1 2 55 56 57 58 61 60 VDD3 VCC RESET# GND V6300C C23 VDD3 0.1u C24 0.1u C25 0.1u C26 0.1u C27 0.1u 5 11 17 25 34 42 49 53 64 VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 2 3 VDD3 RST# GND VDD3 VDD3 VDD3 VDD3 3 10 23 30 37 44 50 54 59 4 51 52 63 48M_XOUT 48M_XIN ACT/LINK /PHY_PWN PHY_PWN /PHY_RST PHY_RST RX_DV RX_ER RXD3 RXD2 RXD1 RXD0 RX_CLK TX_EN TXD3 TXD2 TXD1 TXD0 TX_CLK CRS COL MDIO MDC 25M_CLKO 25M_XIN 25M_XOUT EEDO EEDI EECK EECS /S_RMII /S_MAC /S_FDPX S_EXT SPD_UP 41 40 39 38 32 31 29 28 27 26 24 22 21 20 19 18 16 15 13 14 12 33 35 36 48 47 46 45 43 9 8 7 6 PRST# PRST# RXDV RXD3 RXD2 RXD1 RXD0 RXCLK TXEN TXD3 TXD2 TXD1 TXD0 TXCLK CRS COL MDIO MDC 25MHZ R23 4.7K
VDD3
*1 USB Port Link/Act LED
VDD3 R21 330
/RST LEERDY D+ DTEST0 TEST1 TEST2 /EP78DIS TEST3 TEST4 TEST_OUT VDD VDD VDD VDD VDD VDD VDD VDD VDD
RXDV RXD3 RXD2 RXD1 RXD0 RXCLK TXEN TXD3 TXD2 TXD1 TXD0 TXCLK CRS COL MDIO MDC 25MHZ 25M_XIN 25M_XOUT
DD+ VDD5 GND
S
4 2
3 1
C20 20P
C21 20P
R26
4.7K
U4 C22 0.01u F1 FUSE
VDD3 EEDO EEDI EECK EECS
VDD3
R27 4.7K
R28 4.7K
L4 F.B.
L5 F.B. D6 1N4148 R29 10K RST#
*2 RC reset (option)
C28 0.47u
AX88170 L
U5 VDD3 5V U6 3 VOUT VIN ADJ/GND + C30 47u/16V C33 1000P AMS1117 47u/16V 2 1 + C29 C31 0.1u C32 0.01u GND GND 93C56R VDD3 VDD3 EECS EECK EEDI EEDO 1 2 3 4 CS SK DI DO VCC NC NC GND 8 7 6 5 VDD3
ASIX ELECTRONIC CORPORATION Title AX88170 Size B Date: Document Number 170AP2A.SCH Monday, February 26, 2001 Sheet 2 of 2 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
TXD0 TXD1 TXD2 TXD3 TXCLK TXEN RXD0 RXD1 RXD2 RXD3 RXCLK RXDV COL CRS 25MHZ PRST# MDC MDIO VDD3 GND TXD0 TXD1 TXD2 TXD3 TXCLK TXEN RXD0 RXD1 RXD2 RXD3 RXCLK RXDV COL CRS 25MHZ PRST# MDC MDIO VDD3 GND VDD3 R2 4.7K TXD3 TXD2 TXD1 TXD0 TXEN TXCLK R4 20 RXD3 RXD2 RXD1 RXD0 RXDV RXCLK R7 COL CRS MDIO MDC 25MHZ 23 24 25 26 27 28 37 38 21 22 45 46 36 35 34 33 32 31
USB to Fast Ethernet/HomePNA Controller
Set PHY Address TO 00001 and LED DISPLAY C.K.T. G
U1 TXD3 TXD2 TXD1 TXD0/TXD TX_EN TX_CLK RXD3/PHYAD0 RXD2/CMDDIS# RXD1/HI_POWER_EN# RXD0/RXD/LOW_SPEED_EN# RX_DV/GPSI_SEL# RX_CLK TIP COL/MDIO_INT_EN# CRS/PIN_INTRP_EN# MDIO MDC RBIAS X1 X2 RING 7 8 TIP YELLOW LED RING POWERLED# 4 RED LED R12 9.31K 1% R13 10K R10 R11 10K D4 330 D1 ACTLED# R1 R3 COLLED# R5 R6 SPEEDLED# R8 330 GREEN LED 10K D2 330 YELLOW LED 10K D3 330
VDD3
20
R9 4.7K
VDD3 + C1 47u/16V C2 0.01u C3 0.1u C4 0.1u
VDD3
19 29 39
IO_VDD1 IO_VDD2 CORE_VDD ANA_VDD1 ANA_VDD2 ANA_VDD3
AVDD3_1 L1 VDD3 + C5 47u/16V C7 0.01u F.B. + C6 C8 C9 0.1u
48 5 11
LED_COL/PHYAD2 LED_ACT/PHYAD1 LED_SPEED/PHYAD3 LED_POWER/PHYAD4
17 18 16 15 44
COLLED# ACTLED# SPEEDLED# POWERLED# PRST#
VDD3
47u/16V 0.01u
20 30 L2 VDD3 + C10 47u/16V C12 F.B. 0.01u + C11 C13 AVDD3_2 C14 0.1u 47 3 6 10 1 2 9 40 41
RESET# IO_GND1 IO_GND2 CORE_GND CORE_SUB(0V) ANA_GND1 ANA_GND2 ANA_GND3 ANA_GND4 SUB_GND1 SUB_GND2 SUB_GND3 DP83851C RESERVED RESERVED RESERVED RESERVED RESERVED
R14 49.9
R15 49.9
U2 12 13 14 42 43 TIP RING R16 4.7K R17 0 1 2 3 4 5 6 7 8 + GND NC NC NC NC NC HR002 NC NC NC NC NC NC TIP RING 16 15 14 13 12 11 10 9 1 2 3 4 5 6
J1 NC A1 TIP RING A2 NC RJ11
47u/16V 0.01u
Title HOMENET PHY C.K.T. Size B Date: Document Number 170AP2A1.SCH Monday, February 26, 2001 Sheet 1 of 2 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
USB to Fast Ethernet/HomePNA Controller
Demonstration Circuit C: 4 USB Ports + 1 Ethernet Port Bridge AP
AX88170 L PHY mode application (MII Interface)
VDD5 JP1 1 2 3 4 POWER CONNECTOR (POWER IN: 5V/3A) +5V + C1 200u/16V C4 0.1u C5 1000p L1 F.B. + C2 200u/16V C6 0.1u C7 1000p GND5 GND + 47u/16V 0.1u VDD5 VDD5 C8 C11 3 U1 VOUT VIN ADJ/GND AMS1084-3.3V 47u/16V 0.1u 0.01u GND 2 1 + C3 C9 VDD3 C10
L2 F.B.
VDD5
VDD5 U2A 1 74LV04 2 3 74LV04 U2C 5 VDD3 U5 R4 L3 8 F.B. C12 0.1u C13 1000p OSC 25MHZ 74LV04 U2E 11 10 R6 20 25M_USB3 74HC04 VCC OUT GND 5 4 9 8 R5 20 25M_USB2 25MHZ U2D 5 6 RST_USB# 51 74LV04 U4C 6 R3 20 25M_USB1 U2B 4 R2 20 25M_USB0 U3 VCC RESET# GND V6300F 1 2 3 1 GND 74HC04 74HC04 U4A 2 3 U4B 4 RST_EN# R1 10K
74LV04 VDD5 R7 20 VDD3 VDD5 VDD3 GND 25M_USB0 25M_USB1 25M_USB2 25M_USB3 25M_REP 25M_PHY RST_EN# RST_USB#
U6A 1 2 3
U6B 4 R8 20 25M_REP
*1 R7 & R8 : Adjust ax88875AP LCLK to AX88170 L TXCLK
GND 25M_USB0 25M_USB1
74F04
74F04 U6C
25M_USB2 25M_USB3 25M_REP
5
6
R9
20
25M_PHY 25M_PHY
74F04 R10 20
*2 R9 & R10 : Adjust DM9191F LCLK to AX88875AP LCLK
RST_EN# RST_USB#
Title POWER & RESET C.K.T. Size B Date: Document Number 170AP5A.SCH Monday, February 26, 2001 Sheet 1 of 7 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
VDD3 VDD3 GND VDD3 GND
USB to Fast Ethernet/HomePNA Controller
VDD3
*3 USB Port Link/Act LED
R11 Q1 2SC2412K 1K R13 J1 S USB-CON 4 3 2 1 1.5K R14 R15 L4 F.B. C14 S 20P C15 20P R16 4.7K 18 18 ALDONE D+ D62 1 2 55 56 57 58 61 60 VDD3 VDD3 C16 0.01u VDD3 VDD3 VDD3 C17 0.1u R17 20k C18 0.1u C19 0.1u C20 0.1u C21 0.1u 5 11 17 25 34 42 49 53 64 3 10 23 30 37 44 50 54 59 RST_USB# R12 330 D1 LED RST# 4 ACT/LINK# 63 VDD3 48M_XOUT 48M_XIN 51 52
U7 48M_XOUT 48M_XIN ACT/LINK /RST LEERDY D+ DTEST0 TEST1 TEST2 /EP78DIS TEST3 TEST4 TEST_OUT VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS /HOMELINK GPIO1 /PHY_RST GPIO0 RX_DV RX_ER RXD3 RXD2 RXD1 RXD0 RX_CLK TX_EN TXD3 TXD2 TXD1 TXD0 TX_CLK CRS COL MDIO MDC 25M_CLKO 25M_XIN 25M_XOUT EEDO EEDI EECK EECS /S_RMII /S_MAC /S_FDPX S_EXT SPD_UP 41 40 39 38 32 31 29 28 27 26 24 22 21 20 19 18 16 15 13 14 12 33 35 36 48 47 46 45 43 9 8 7 6 EEDO EEDI EECK EECS R18 R19 10K 10K 25M_USB0 RXDV RXD3 RXD2 RXD1 RXD0 RXCLK TXEN TXD3 TXD2 TXD1 TXD0 CRS RXDV0 RXD03 RXD02 RXD01 RXD00 RXCLK0 TXEN0 TXD03 TXD02 TXD01 TXD00 CRS0
DD+ VDD5 GND
4 2
3 1
VDD3
48M_XIN L5 2.2uH C22 8p
Y1 48M
R20 48M_XOUT 0 C23 8p
AX88170 L
C24 22pF U8 EECS EECK EEDI EEDO 1 2 3 4 CS SK DI DO 93C56R VCC NC NC GND 8 7 6 5 VDD3
ASIX ELECTRONIC CORPORATION Title AX88170 CIRCUIT 1 Size B Date: Document Number 170AP5A1.SCH Monday, February 26, 2001 Sheet 2 of 7 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
VDD3 VDD3 GND VDD3 GND
USB to Fast Ethernet/HomePNA Controller
VDD3
*4 USB Port Link/Act LED
R21 Q2 2SC2412K 1K R23 J2 S USB-CON 4 3 2 1 1.5K R24 R25 L6 F.B. C25 S 20P C26 20P R26 4.7K 18 18 ALDONE D+ D62 1 2 55 56 57 58 61 60 VDD3 VDD3 C27 0.01u VDD3 VDD3 VDD3 C28 0.1u R27 20k C29 0.1u C30 0.1u C31 0.1u C32 0.1u 5 11 17 25 34 42 49 53 64 3 10 23 30 37 44 50 54 59 RST_USB# R22 330 D2 LED RST# 4 ACT/LINK# 63 VDD3 48M_XOUT 48M_XIN 51 52
U9 48M_XOUT 48M_XIN ACT/LINK /RST LEERDY D+ DTEST0 TEST1 TEST2 /EP78DIS TEST3 TEST4 TEST_OUT VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS /HOMELINK GPIO1 /PHY_RST GPIO0 RX_DV RX_ER RXD3 RXD2 RXD1 RXD0 RX_CLK TX_EN TXD3 TXD2 TXD1 TXD0 TX_CLK CRS COL MDIO MDC 25M_CLKO 25M_XIN 25M_XOUT EEDO EEDI EECK EECS /S_RMII /S_MAC /S_FDPX S_EXT SPD_UP 41 40 39 38 32 31 29 28 27 26 24 22 21 20 19 18 16 15 13 14 12 33 35 36 48 47 46 45 43 9 8 7 6 EEDO EEDI EECK EECS R28 R29 10K 10K 25M_USB1 RXDV RXD3 RXD2 RXD1 RXD0 RXCLK TXEN TXD3 TXD2 TXD1 TXD0 CRS RXDV1 RXD13 RXD12 RXD11 RXD10 RXCLK1 TXEN1 TXD13 TXD12 TXD11 TXD10 CRS1
DD+ VDD5 GND
4 2
3 1
VDD3
48M_XIN L7 2.2uH C33 8p
Y2 48M
R30 48M_XOUT 0 C34 8p
AX88170 L
C35 22pF U10 EECS EECK EEDI EEDO 1 2 3 4 CS SK DI DO 93C56R VCC NC NC GND 8 7 6 5 VDD3
ASIX ELECTRONIC CORPORATION Title AX88170 CIRCUIT 2 Size B Date: Document Number 170AP5A2.SCH Monday, February 26, 2001 Sheet 3 of 7 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
VDD3 VDD3 GND VDD3 GND
USB to Fast Ethernet/HomePNA Controller
VDD3
*5 USB Port Link/Act LED
R31 Q3 2SC2412K 1K R33 J3 S USB-CON 4 3 2 1 1.5K R34 R35 L8 F.B. C36 S 20P C37 20P R36 4.7K 18 18 ALDONE D+ D62 1 2 55 56 57 58 61 60 VDD3 VDD3 C38 0.01u VDD3 VDD3 VDD3 C39 0.1u R37 20k C40 0.1u C41 0.1u C42 0.1u C43 0.1u 5 11 17 25 34 42 49 53 64 3 10 23 30 37 44 50 54 59 RST_USB# R32 330 D3 LED RST# 4 ACT/LINK# 63 VDD3 48M_XOUT 48M_XIN 51 52
U11 48M_XOUT 48M_XIN ACT/LINK /RST LEERDY D+ DTEST0 TEST1 TEST2 /EP78DIS TEST3 TEST4 TEST_OUT VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS /HOMELINK GPIO1 /PHY_RST GPIO0 RX_DV RX_ER RXD3 RXD2 RXD1 RXD0 RX_CLK TX_EN TXD3 TXD2 TXD1 TXD0 TX_CLK CRS COL MDIO MDC 25M_CLKO 41 40 39 38 32 31 29 28 27 26 24 22 21 20 19 18 16 15 13 14 12 33 25M_USB2 EEDO EEDI EECK EECS R38 R39 10K 10K RXDV RXD3 RXD2 RXD1 RXD0 RXCLK TXEN TXD3 TXD2 TXD1 TXD0 CRS RXDV2 RXD23 RXD22 RXD21 RXD20 RXCLK2 TXEN2 TXD23 TXD22 TXD21 TXD20 CRS2
DD+ VDD5 GND
4 2
3 1
25M_XIN 35 36 25M_XOUT 48 EEDO 47 EEDI 46 EECK 45 EECS /S_RMII /S_MAC /S_FDPX S_EXT SPD_UP 43 9 8 7 6
VDD3
48M_XIN L9 2.2uH C44 8p
Y3 48M
R40 48M_XOUT 0 C45 8p
AX88170 L
C46 22pF U12 EECS EECK EEDI EEDO 1 2 3 4 CS SK DI DO 93C56R VCC NC NC GND 8 7 6 5 VDD3
ASIX ELECTRONIC CORPORATION Title AX88170 CIRCUIT 3 Size B Date: Document Number 170AP5A3.SCH Monday, February 26, 2001 Sheet 4 of 7 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
VDD3 VDD3 GND VDD3 GND
USB to Fast Ethernet/HomePNA Controller
VDD3
*6 USB Port Link/Act LED
U13 R41 VDD3 R42 1K R43 330 D4 RST_USB# LED RST# ALDONE D+ D4 62 1 2 55 56 57 58 61 60 VDD3 VDD3 3 10 23 30 37 44 50 54 59 5 11 17 25 34 42 49 53 64 48M_XOUT 48M_XIN ACT/LINK# 51 52 63 48M_XOUT 48M_XIN ACT/LINK /RST LEERDY D+ DTEST0 TEST1 TEST2 /EP78DIS TEST3 TEST4 TEST_OUT VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS /HOMELINK GPIO1 /PHY_RST GPIO0 RX_DV RX_ER RXD3 RXD2 RXD1 RXD0 RX_CLK TX_EN TXD3 TXD2 TXD1 TXD0 TX_CLK CRS COL MDIO MDC 25M_CLKO 25M_XIN 25M_XOUT EEDO EEDI EECK EECS /S_RMII /S_MAC /S_FDPX S_EXT SPD_UP 41 40 39 38 32 31 29 28 27 26 24 22 21 20 19 18 16 15 13 14 12 33 35 36 48 47 46 45 43 9 8 7 6 EEDO EEDI EECK EECS R48 R49 10K 10K 25M_USB3 RXDV RXD3 RXD2 RXD1 RXD0 RXCLK TXEN TXD3 TXD2 TXD1 TXD0 CRS RXDV3 RXD33 RXD32 RXD31 RXD30 RXCLK3 TXEN3 TXD33 TXD32 TXD31 TXD30 CRS3
Q4 2SC2412K
J4 S
USB-CON 4 3 2 1
1.5K R44 R45 L10 F.B. C47 20P C48 20P R46 4.7K 18 18
DD+ VDD5 GND
S C49 0.01u
4 2
3 1
VDD3 VDD3 VDD3 C50 0.1u R47 20k C51 0.1u C52 0.1u C53 0.1u C54 0.1u
VDD3
48M_XIN L11 2.2uH C55 8p
Y4 48M
R50 48M_XOUT 0 C56 8p
AX88170 L
C57 22pF U14 EECS EECK EEDI EEDO 1 2 3 4 CS SK DI DO 93C56R VCC NC NC GND 8 7 6 5 VDD3
ASIX ELECTRONIC CORPORATION Title AX88170 CIRCUIT 4 Size B Date: Document Number 170AP5A4.SCH Monday, February 26, 2001 Sheet 5 of 7 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
U15 VDD5 RXD12 RXD13 TXEN1 TXD10 TXD11 TXD12 TXD13 GND R56 R57 R59 10K 10K VDD5 GND 10K RXDV2 CRS2 RXCLK2 RXD20 RXD21 RXD22 RXD23 TXEN2 TXD20 TXD21 TXD22 TXD23 GND R65 10K RXDV3 CRS3 RXCLK3 RXD30 RXD31 RXD32 RXD33 TXEN3 TXD30 TXD31 TXD32 TXD33 GND R67 R68 10K DISFC# MODE0 10K VDD5 RXER4 RXDV4 CRS4 RXCLK4 RXD40 RXD41 RXD42 RXD43 TXEN4 TXD40 TXD41 TXD42 TXD43 TXER4 R66 20 R60 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VDD RXD<1><2> RXD<1><3> TXEN<1> TXD<1><0> TXD<1><1> TXD<1><2> TXD<1><3> TXER<1> COL<1> VSS PULL_DN PULL_DN VDD VSS RXER<2> RXDV<2> CRS<2> RXCLK<2> RXD<2><0> RXD<2><1> RXD<2><2> RXD<2><3> TXEN<2> TXD<2><0> TXD<2><1> TXD<2><2> TXD<2><3> TXER<2> COL<2> VSS RXER<3> RXDV<3> CRS<3> RXCLK<3> RXD<3><0> RXD<3><1> RXD<3><2> RXD<3><3> VDD TXEN<3> TXD<3><0> TXD<3><1> TXD<3><2> TXD<3><3> TXER3<3> COL<3> VSS PULL_DN EN_FLOW-CTL MODE TXE_DELAY VDD RXER<4> RXDV<4> CRS<4> VSS VDD RXCLK<4> RXD<4><0> RXD<4><1> RXD<4><2> RXD<4><3> TXEN<4> TXD<4><0> MEM_SIZE<0> TXD<4><1> MEM_SIZE<1> TXD<4><2> ENTRIES TXD<4><3> ST_FW TXER<4> COL<4> COL_O<4> VSS /LCOL100 MDC MDO MCLK /BMA<15> /LUTI<0> /LUTI<1> /LUTI<2> /LUTI<3> /BMWR /IR_ACT_EN BMA<8> BMA<9> AX88875AP
USB to Fast Ethernet/HomePNA Controller
RXD<1><1> RXD<1><0> RXCLK<1> CRS<1> RXDV<1> RXER<1> COL<0> TXER<0> TXD<0><3> TXD<0><2> TXD<0><1> TXD<0><0> TXEN<0> VSS RXD<0><3> RXD<0><2> RXD<0><1> RXD<0><0> RXCLK<0> CRS<0> RXDV<0> RXER<0> VSS VDD PULL_DN PULL_DN VDD /HALF10 LCLK VSS /RST TEST1 NC /LACT<1> /LACT<0> NC VDD /LACT<3> /LACT<2> NC /LACT<4> VSS /LPART<4> LPART<3> /LPART<2> /LPART<1> /LPART<0> /TEST2 /LUTI<4> /LUTI<5> /LCOL10 /LSEL10 VDD VSS BMA<7> BMA<6> BMA<5> BMA<4> VDD BMA<3> BMA<2> BMA<1> BMA<0> VSS BMD<7> BMD<6> BMD<5> BMD<4> BMD<3> BMD<2> BMD<1> BMD<0> VSS BMA<16> BMA<15> BMA<14> BMA<13> BMA<12> BMA<11> BMA<10> VDD 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 R51 20 RXD11 RXD10 RXCLK1 CRS1 RXDV1 TXD03 TXD02 TXD01 TXD00 TXEN0 RXD03 RXD02 RXD01 RXD00 RXCLK0 CRS0 RXDV0 R62 GND VDD5 VDD5 LCLK GND RST# R63 R64 10K 10K U16 25M_REP RST_EN# MA16 MA14 MA12 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD0 MD1 MD2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N.C. A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS HSRAM128*8 VCC A15 CS2 WE_# A13 A8 A9 A11 OE_# A10 CS1_# I/O8 I/O7 I/O6 I/O5 I/O4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD5 MA15 VDD5 MWR# MA13 MA8 MA9 MA11 GND MA10 GND MD7 MD6 MD5 MD4 MD3 10K R52 10K R53 R54 R55 R58 10K 10K 10K 10K MEMS1 ENTRY DISFC# MODE0
*7 Set memory size to 128KB High : 256 Low : 1024 *9 LOW: DIS_FLOW-CONTROL *10 settingt to mode 0 *8 ENTRIES Setting :
GND
R61
20
VDD5
LLED4 GND GND
COL10# VDD5 VDD5 GND MA7 MA6 MA5 MA4 VDD5 MA3 MA2 MA1 MA0 GND MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 GND MA16 MA15 MA14 MA13 MA12 MA11 MA10 VDD5 D5 COL10# D6 COL100# LED LED
GND VDD5 R70 20
R69 510 R71 510 100 GLOBAL COLLISION 10 GLOBAL COLLISION
MEMS0 MEMS1 ENTRY ST_FW GND COL100#
VDD5 C58 + 100u/16V GND 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71
R72
10K
MWR# MA8 MA9
Title AX88875 AP C.K.T. Size B Date: Document Number 170AP5A5.SCH Monday, February 26, 2001 Sheet 6 of 7 Rev 2.0
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ASIX ELECTRONICS CORPORATION
AX88170
VDD5 GND LLED4 25M_PHY RST_EN# VDD5 GND LLED4 25M_PHY RST# AGND AVDD5 RDN RDP CRS4 RXER4 RXDV4 RXCLK4 RXD40 RXD41 RXD42 RXD43 TXEN4 TXER4 TXD40 TXD41 TXD42 TXD43 CRS RXER RXDV RXCLK AGND RXD0 RXD1 RXD2 RXD3 TXEN TXER TXD0 TXD1 R81 TXD2 AGND TXD3 6.2K (1%) GND VDD5 GND AGND TDN TDP AVDD5 25M_PHY AGND AVDD5 AVDD5 AGND AVDD5 AGND TDN TDP AVDD5 AVDD5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 U17 AVCC NC NC NC NC AGND AVCC AVCC RXIRXI+ AGND AGND 10TXO10TXO+ AVCC AVCC AGND AGND NC NC AVCC AVCC AGND AGND 100TXO100TXO+ AVCC DVCC OSC/X1 X2 DGND OSC/XLT# AVCC AGND BGRES NC DGND DGND AGND AVCC TRIDRV UTP SPEED10 RX_LOCK DGND NC LINKSTS CLK25M DVCC FDXLED# DM9191F
USB to Fast Ethernet/HomePNA Controller
AGND AGND 10BTSER BPSCR BP4B5B BPALIGN RPTR/NODE# OPMODE3 OPMODE2 OPMODE1 OPMODE0 PHYAD4 PHYAD3 DVCC DGND PHYAD2 PHYAD1 PHYAD0 TESTDOME RESET# RX_EN RX_ER/RXD4 RX_DV COL CRS RX_CLK DVCC DGND RXD0 RXD1 RXD2 RXD3 DVCC DGND MDIO MDC TX_CLK TX_EN DVCC DGND TXD0 TXD1 TXD2 TXD3 TX_ER/TXD4 TXLED# RXLED# LINKLED# DGND COLLED# 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AGND
TX 1CT:1CT RX 1CT:1CT
AVDD5 C72 0.1u R73 49.9 TDP TDN RDP R74 49.9 T1 16 14 15 1 3 2 R75 49.9 R76 49.9 R77 C74 0.1u C75 0.1u R78 R79 16 14 15 1 3 2 16ST8515 10 12 11 7 5 6 10 12 11 7 5 6 RJ03 RJ06 RJ01
RJ03 RJ06 RJ01 RJ02
GND VDD5 VDD5 VDD5 VDD5 VDD5 GND GND VDD5 GND VDD5 GND RST# VDD5 RXER RXDV CRS RXCLK VDD5 GND RXD0 RXD1 RXD2 RXD3 VDD5 GND
JP2 1 2 3 4 5 6 7 8 RJ45
(ETHERNET
UPLINK POART)
(ETHERNET PORT) JP3 RJ01 RJ02 RJ03 RJ06 RJ02 75 75 75 75 R80 C73 GND_E 0.01u/2KV C76 GND 0.01u CHASSIS 1 2 3 4 5 6 7 8 RJ45
RDN
GND
TXEN VDD5 GND TXD0 TXD1 TXD2 TXD3 TXER LLED GND R82 510 D7 GREEN LED LLED4 Ethernet Port Link/Act LED
VDD5
VDD5
L12 F.B. C78 1000p C79 1000p C77 + 47u/16V 0.1u C80
AVDD5 C81 0.1u AGND C82 0.1u C83 0.1u C84 0.1u C85 0.1u
GND
VDD5 C86 + 47u/16V GND Title EtherNet PHY C.K.T. Size B Date: Document Number 170AP5A6.SCH Monday, February 26, 2001 Sheet 7 of 7 Rev 2.0 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u C87 C88 C89 C90 C91 C92 C93
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ASIX ELECTRONICS CORPORATION

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